The present invention relates, in general, to stack packaging of integrated circuits and, more particularly, to stacked bus packages for integrated circuits.
Previous stack packaged IC devices are limited to the standard number of leads on the IC package. See U.S. Pat. Nos. 3,370,203, 4,116,519 and 4,437,718.This limits the number of different types of chips that may be stacked. In the prior art the type of chips to be stacked must be of the same type (e.g. all memory chips). Because of the limited number of lines, you would not be able to incorporate a microprocessor in a stack with memory chips, digital to analog convertors, or other non lead compatible devices.